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History and Timescales
- Long series of hardware demonstrators
- Level 1 produced its TDR in June 1998
- Now mostly in ``fully specified prototype'' phase
(ie different phase from DAQ/HLT)
- Test new subsystems separately up to mid 2001
- Level 1 complete slice(s) starting mid/late 2001
- Priority: level 1 trigger decision path
- On successful completion of at least a minimal
set of internal slice tests,
join DAQ/HLT integrated slice mid 2002
- Though some ROD-RoIB and ROD-ROS tests early 2001
- Also need integrated tests with calorimeters and muon chambers
Murrough Landon (m.p.j.landon@qmw.ac.uk)